Experimental Evaluation and Optimization of GaN Inverter for Motor Drive Applications

In motor control applications, the use of Gallium Nitride devices (GaN FET) allows an increase in the switching frequency and a significant reduction in dead time. In recent studies on electric drives with GaN devices, it has been found that increasing the frequency and reducing the dead time leads to higher motor efficiency [1]. This paper deals with the experimental analysis of the basic switching cell topology in an inverter for motor control with GaN devices. GaN devices are faster than conventional MOSFETs or IGBTs, and it is standard practice to use several capacitors on the switching cell to damp the ringing of the switching node. High frequency capacitors are placed near the GaN devices in the same layer, middle frequency capacitors are placed in the opposite layer, and finally the DC bank capacitors are electrolytics. Commonly the DC bank capacitors are over-sized [2].

The paper describes the tests done to optimize a 48V GaN inverter running a motor with 50 A peak sinusoidal output phase current. An introduction on how to calibrate the measurement system (passive probes and oscilloscope) is also included. The paper is divided in several sections showing the effect of the high frequency capacitors, the effect of the middle frequency capacitors, and the effect of the DC capacitors. In particular, the DC capacitor effect is analyzed at different PWM frequencies from 20 kHz to 100 kHz, discussing the real total capacitance need for the GaN inverter. Finally, in the full paper, the PCB layout practice to reduce ringing and EMI is explained.

Knowing that increasing the PWM frequency and reducing the dead time in a motor inverter application increases the motor efficiency [2], the paper shows that with a total of 90 F DC bus bank capacitors, no high frequency and no middle frequency capacitors, and a good layout, a GaN inverter at PWM frequency of 100 kHz can run smoothly a motor with 50 A pk phase current.